Flatness & Nanotopography -- Impact of the Wafer

Nanotopography of the silicon wafer is dictated to a large extent by the polishing process. For single-sided polished (SSP) wafers, the polishing process has been optimized to minimize nanotopography. In this process, to achieve good flatness, the wafer must be mounted or chucked against a flat reference block. Since the wafer backside is etched (not polished smooth), it has surface topology. Because of the fixturing process used to mount the wafers (e.g. wax mounting or vacuum chucking), the topology of the backside of the wafer and the fixturing surface and or adhesive/wax are transmitted to the front side and causes nanotopography.. The other technique of mounting a wafer (the one that is normally used in CMP), viz. free mounting, does not cause nanotopography formation, but also does not guarantee the wafer is made flat. Since flatness can also be critical for device manufacture (lithography), it is difficult to produce good, low nanotopography and good, low flatness with conventional SSP.

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