• PMOS Ion increases by 10-20%

• No degradation in NMOS

• No fab integration issues or process changes are needed... wafer is still (100) surface orientation

• Applicable to multiple platforms including standard bulk wafers, SOI, and strained wafers

CMOS transistor scaling progress has been enabled by continuous reductions in channel length and gate dielectric thickness. In the sub-100nm MOSFET transistor scaling regime, fundamental limits in channel length and gate dielectric scaling are being encountered. The primary barriers to continuing scaling of planar CMOS transistors are short channel effects (SCE), which are increasingly limiting the transistor drive current improvement, and leakage current through the very thin gate dielectric. In order to manage SCE, the channel doping continues to increase. But, increasing the channel doping degrades mobility by introducing more charged impurity scattering sites. Also, the future implementation of high-K gate dielectric for control of gate leakage is known to degrade channel mobility. Because MOSFET drive current also depends on the mobility of charge carriers in the channel of the device, enabling a mobility enhancement in the device channel can offer a means to offset the negative aspects of managing SCE and gate leakage. Mobility, which describes the ease in which charge carriers drift in a semiconductor, is inversely proportional to carrier mass. Enhancing mobility (µ) enables higher MOSFET drive current which leads to higher device speed as described by the functional relationships shown below.
Mobility enhancement methods are the subject of an intense investigation at the starting wafer level and in the device fabrication process. The main approaches for enhancing mobility at the starting wafer level are by changing the orientation of the wafer notch, changing the wafer surface orientation, and straining the device channel. Table 1 highlights the mobility enhancement options available at the starting wafer level. The change in notch orientation from <110> to <100> is a drop-in solution that enables a 10-20% enhancement in PMOS operating current.

Several studies published in scientific literature demonstrate that orienting the PMOS channel along the <100> direction on (100) surface orientation wafers results in a gain of 10-20% in the transistor drive or “on current”(1-3). No degradation has been observed on NMOS transistors. The re-orientation of the channel directions is more easily realized by changing the starting wafer than by modifying the transistor layout methodology. The mechanism for the gain in PMOS drive current is increased mobility due to the reduction in the effective mass of holes moving along the <100> direction.

Orienting the channel direction along <100> is a simple process change in the starting wafer fabrication. Historically, the wafer flat or notch on (100) surface orientation wafer has been formed along the <110> direction at crystal grinding because these directions define the easily cleaved crystal directions of a (100) surface orientation wafer. However, since wafer dicing is done by sawing through the scribe lines orienting along <110> is no longer a technological requirement. Figure 1 shows the simple process change for rotating the crystal piece by 45 degrees at crystal grinding in order to form the wafer notch or flat along the <100> direction.

The orientation of the CMOS channel along the <100> direction offers a simple, low cost, low risk production proven enhancement of the PMOS transistor with no degradation to the NMOS transistor or complications in device process integration. It can be applied to all starting material platforms including advanced polished wafers, epitaxial wafers, and SOI wafers. The <100> notch option is already a high volume wafer fabrication process. It is a production proven starting wafer option for enhancing the performance of sub-100nm CMOS technologies. Beyond the CMOS applicability described in this note, the reorientation of the notch position to <100> has also been reported to enable improvement in the DRAM deep trench capacitor shape profiles etched into the silicon substrate, increasing cell capacitance by ~ 25%(4).

References:

1. R. Khamankar et al., 2004 Symposium on VLSI Technology Digest of Technical Papers, pg 162.
2. T. Matsumoto et al., 2002 IEDM Digest of Technical Papers, pg 663.
3. T. Komoda et al., 2004 IEDM Digest of Technical Papers, pg 217.
4. J. Amon et al., 2004 IEDM Digest of Technical Papers, pg 73.