The table below is designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications. Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues. Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided. Simply click on the MEMC product logo or any embedded link in the table to access more information on that subject. You may also choose to click on the “Segment Description” link to access a more detailed segment overview.
Segment
Drivers
|
Bulk
Surface
Integration
|
Problem
|
Solution
|
MEMC
Product
(or Process)
|
Benefits
|
Critical
Dimension
Scaling
|
S
|
Maintain dimension scaling to increase performance and functionality
|
Advanced Single Side Polish (200mm)
|
Integration of ultra-flat wafer processing with:
Ar-Annealed
Epi (P/P+)
|
Enable dimension scaling with high device yield.
|
| Device Yield
|
S, B
|
Eliminate wafer defect-related device yield loss
|
COP-free wafer with Internal Gettering and Oxygen Precipitate-free zone.
|
Ar-Annealed
Epi (P/P+)
|
High Device Yield.
|
| Radio Frequency CMOS
|
S, B, I
|
Integrate high quality factor passive components and isolate RF/analog components from digital CMOS
|
High resistivity silicon
High resistivity silicon on insulator
|
Ar-Annealed
|
~ 100% increase in inductor Q-factor for 10x increase in resistivity
|
| Enhance Performance
|
S, I
|
Increase transistor drive current to increase operating frequency.
|
<100> notch / channel orientation
|
Ar-Annealed
Epi (P/P+)
|
10% PMOS drive current enhancement through improved channel mobility
|
B - Bulk; this refers to the entire lateral and vertical region between the wafer front and back sides
S - Surface; the surface region of a silicon wafer (usually refers to the top 10µ)
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufacturers line
|
