The table below is designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications. Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues. Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided. Simply click on the MEMC product logo or any embedded link in the table to access more information on that subject. You may also choose to click on the “Segment Description” link to access a more detailed segment overview.
Segment
Drivers
|
Bulk
Surface
Integration
|
Problem
|
Solution
|
MEMC
Product
(or Process)
|
Benefits
|
Enhance Reliability,
Device Yield
|
B, S, I
|
Tunnel Oxide quality is a critical requirement for flash. Killer defect for leakage failure is point defect such as COP and Metal precipitation on TNOX layer
|
COP-free wafer with MDZ. COP-free translates to defect-free material
|
|
MDZ provides robust gettering, which prevents metal contamination
Optia provides COP-free options as Perfect Silicon
|
Enhance Reliability,
Device Yield
|
B, I
|
Flash device is extremely sensitive to COP defects and metal contamination. Therefore, GOI is a critical concern
|
COP-free wafer with MDZ. COP-free translates to defect-free material
|
|
MDZ provides robust gettering, which prevents metal contamination
Optia provides COP-free options as Perfect Silicon
|
| Device Yield
|
B, I
|
Metal Contamination from backside grinding or dry-polishing
|
P/P+ Epi provides good gettering solution
|
P/P+ Epi
|
1. P+ material has minimum gettering requirement
2. A polished wafer provides a cost advantage (Optia)
Optia has epi-like GOI and COP-free characteristics
MDZ provides robust gettering, which prevents metal contamination
|
| Device Yield
|
B, I
|
Yield loss due to gate oxide integrity (GOI) issues.
|
Rapid thermal process based technology in which the oxygen precipitation behavior is controlled by manipulation of vacancy rather than oxygen concentration profiles.
|
|
Yield improvement up to 10%
|
| Processing Cost
|
B, I
|
Increased processing costs due to long thermal treatments.
|
Optia wafers do not rely on long thermal treatments in the IC fab process.
|
|
Reduce thermal budget up to 40%
MDZ reduces cost of ownership (COO) due to lower thermal budget in the IC fab
|
| Enhance Reliability
|
B,S, I
|
Device loss due to metal contamination.
|
Optia will effectively getter high levels of metals such as Copper, Nickel, and Iron.
|
|
Improvement in device reliability
|
| Device Yield
|
B,S, I
|
Crystal defect related yield and reliability degradation.
|
Elimination of harmful crystal defects in the surface and bulk.
|
|
Yield improvement, reliability improvement.
Perfect Silicon crystal results in a defect-free wafer.
|
| Device Yield
|
B, I
|
Yield loss due to uncontrolled precipitation of oxygen.
|
Rapid thermal process based technology in which the oxygen precipitation behavior is controlled by manipulation of vacancy rather than oxygen concentration profiles.
|
|
MDZ provides required BMD densities that demonstrate uniform stacking faults and precipitate distribution.
|
| Device Yield
|
S, I
|
Nanotopography and flatness issues
|
Need uniform flatness center-to-edge to print very small feature sizes.
|
|
Extend usable edge area, which increases the number of usable die per wafer.
|
Enhance Reliablity,
Device Yield
|
B, I
|
Stored charge leakage due to tunnel oxide quality.
|
COP-free wafer with MDZ and OOBG.
|
|
Yield improvement, reliability improvement.
|
B - Bulk; this refers to the entire lateral and vertical region between the wafer front and back sides
S - Surface; the surface region of a silicon wafer (usually refers to the top 10µ)
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufacturers line
|
