Although the silicon wafer is strong at room temperature, it becomes weaker as the temperature is increased. During the furnace processing steps that are necessary for the fabrication of integrated circuits (ICs), a nonuniform elevated temperature produces a nonuniform expansion within the wafer and the resulting thermal stress can cause local or widespread furnace slip. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. The dislocations that are produced by slip can cause junction leakage, premature breakdown, gate oxide integrity failure, and other problems. The physical deformation of the wafer can cause pattern misalignment, focus, and chucking problems, as well as wafer breakage.
A nonuniform temperature is produced in the wafer during furnace push and temperature ramp-up as the radiant energy from the furnace tube heats up the wafer edge faster than the wafer center. This can cause slip around the wafer edge and warp the wafer into a saddle shape (Figure 1).
During temperature ramp-down and furnace pull, the wafer cools faster at the edge than in the center, and this temperature nonuniformity can create slip in the wafer center and cause the wafer to bow (Figure 2).
Decades of fabricating ICs on silicon wafers have shown that furnace slip is always a problem. This is because the fabrication engineer is always faced with the conflicting goals of increasing the speed of furnace temperature ramps and push-pull steps to maximize the furnace throughput, while at the same time limiting the speed of temperature ramps and push-pull steps to prevent wafer warpage and the creation of yield-killing slip dislocations. Each time the wafer diameter increases, a new balance must be found. Each time a new IC technology creates additional built-in device stress, the balance shifts. For example, when oxide-filled shallow trench isolation (STI) structures were introduced, furnace recipes which had previously produced slip-free wafers became recipes which produced massive furnace slip. During thermal cycling, the stress the oxide exerted on the trench side-walls plus the thermal stress due to temperature nonuniformities in the wafer added together to create slip dislocations and to move those dislocations into leakage-sensitive parts of the IC device. But by moderating both the built-in IC device stress and the furnace stress, IC devices with STI structures are now being fabricated successfully.
Temperature is primary factor that controls the strength of the silicon wafer, and this must be taken into account when setting furnace push/pull and temperature ramping conditions. The strength of the wafer decreases significantly at its temperature is increased from 750°C to 800°C. If wafers are pushed into or pulled from a furnace tube set at 750°C, wafer slip is almost never a problem, but if they are pushed or pulled with the tube set at 800°C, slip is almost always a problem. The strength of the wafer decreases further as its temperature is increased further. To prevent wafer slip during furnace temperature ramping, it is necessary to use lower and lower ramping rates for higher and higher temperature ranges. Recommended ramp rates for 200 mm wafers are given in "How to Prevent Furnace Slip." Smaller diameter wafers can be ramped slightly faster, but 300 mm wafers must be ramped more slowly.
Other factors also affect the strength of the silicon wafer. The higher the density of dislocations in a wafer, the weaker the wafer. It takes a considerable stress to create a dislocation, but it only takes a small stress to cause an existing dislocation to move or multiply. The higher the interstitial (dissolved) oxygen concentration, the stronger the wafer. Interstitial oxygen atoms attach themselves to dislocations and prevent them from moving or multiplying. However, the higher the amount of precipitated oxygen, the weaker the wafer. Growing oxygen precipitates use up the interstitial oxygen and punch out new dislocations. The higher the concentration of dopant atoms, the stronger the silicon wafer. The strain fields around atoms, which are larger or smaller than the silicon atoms, impede the motion of dislocations. IC films can exert stress on the underlying silicon and make slip more likely. Trench and other IC structures, as well as mechanical damage sites, weaken the wafer by acting as stress concentrators.
Even though the silicon wafer is weakened by IC fabrication processing, high yielding IC processing is certainly possible if one pays attention to furnace slip and wafer strength issues.