Why Higher Resistivity Wafers?
Normal silicon wafer substrate resistivity ranges for CMOS technologies have typically spanned from a low of about 5 mohm-cm on heavily doped epi substrates to a high of around 30 ohm-cm on polished wafers. Although heavily doped substrates have proven useful for protection against latch-up, digital CMOS device design and performance has not been strongly coupled directly to substrate resistivity. This is changing in the emerging area of CMOS integration of radio frequency transceiver devices operating in the GHz frequency range.
Wireless chip designs can benefit significantly from higher substrate resistivity levels. Improvements in the performance of passive components, such as inductors, and substrate electrical isolation between the integrated digital, RF (radio frequency), and analog components are possible with higher resistivity silicon substrates Substrate resistivities greater than 40 ohm-cm are required now and in some cases resistivities in excess of 1000 ohm-cm will be needed.
High Resistivity Wafer Requirements
Key characteristics of a high resistivity or ultra-high resistivity silicon wafer are 1) a uniform resistivity through the thickness of the wafer, 2) acceptable radial and axial resistivity gradients, and 3) a resistivity that remains stable throughout device processing. These characteristics are dependent on crystal growth and the control of oxygen behavior.
To support RF-CMOS process technologies scaled to the 0.1um design rule and smaller, wafers must be available in large diameter sizes like 200mm and 300mm, and must support all the advanced wafer parametrics such as site flatness and nanotopography. Wafers must also be available in a COP-free form to achieve a very low wafer defect density for high yielding, highly integrated devices (COP is vacancy agglomerated defect from crystal growth that intersects final wafer surface). The additional capability for metallic gettering protection via oxygen precipitates is also desirable. CZ products such as Optia (COP-free polished wafer enhanced with MDZ), Aegis (P/P- epi wafer enhanced with MDZ), or Ar-Annealed wafers are best positioned to satisfy all these requirements for the case of high resistivity wafers up to 100ohm-cm. High resistivity wafers up to 100 ohm-cm are currently used in RF applications and satisfy the current performance requirements.
As wireless standards move to even higher GHz range frequencies, ultra-high resistivity wafers will be needed in order to maintain acceptable inductor quality factors and to minimize cross-talk between transistors. It's expected that the ultra-high resistivity requirement will emerge in the 2004-2005 timeframe. Ultra-high resistivity wafers into the 1000 ohm-cm range pose some additional challenges for CZ wafers that will be discussed in the next sections.